d-Matrix hits 100 TB/s

At Hot Chips 2026, d-Matrix presented an AI accelerator that attacks the memory wall by stacking compute directly on custom DRAM. The design uses a TSMC 4nm compute die bonded face-to-face on a purpose-built memory die at a 36-micron pitch, targeting 100 TB/s of bandwidth per card. That is the kind of architectural swing startups must take to challenge GPU incumbents: inference and generative workloads are increasingly constrained by moving data, not just math throughput. If d-Matrix can translate the packaging demo into production economics, it gives cloud and enterprise buyers a credible alternative path for lower-latency AI serving.

Sources from the briefing

• Hot Chips 2026: d-Matrix stacks AI accelerator directly on custom DRAM for 100 TB/s per card — TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed die - Tom's HardwareTom's Hardware