
Tech • IA • Crypto
Huawei is promoting a new chip scaling paradigm focused on signal efficiency rather than transistor size, challenging decades of semiconductor industry norms.
For nearly 60 years, the semiconductor industry has followed Moore’s Law, measuring progress by shrinking transistor size from 5 nm to 3 nm and soon 2 nm. This approach defined technological leadership and profitability. However, diminishing returns and rising manufacturing complexity have made further miniaturization increasingly costly and less effective.
Since 2019, the United States has restricted Huawei’s access to advanced chipmaking tools, notably EUV lithography machines produced by ASML. Without these, China’s top foundry SMIC remains limited to older processes around 7 nm, leaving a structural gap of up to 10–15 years compared to leading players.
In response, Huawei introduced a new framework known as the “Tao Scaling Law”, shifting focus from transistor size to signal transmission efficiency. The approach highlights the growing importance of interconnections, which now account for over 75% of signal delay in advanced chips, according to industry data.
Huawei’s solution centers on logic folding, a method of stacking circuits vertically rather than spreading them across a flat surface. With संपर्क points spaced as tightly as 1.5 microns, stacked layers function as a unified circuit. This reduces signal travel distance, lowering resistance and improving speed.
Huawei reports gains of 55% higher density and 41% improved energy efficiency using this method, though these figures lack independent verification. The first commercial use is المتوقع in Kirin chips expected in late 2026, likely targeting high-end smartphones.
Instead of equating advancement with smaller nodes, Huawei proposes measuring performance by signal delay and efficiency. This reframing could weaken the strategic importance of EUV technology, long controlled by Western supply chains.
The announcement boosted SMIC’s stock by over 7%, reflecting investor optimism. More broadly, it signals an attempt by a Chinese firm to establish a new global benchmark, influencing capital allocation, research priorities, and industrial policy.
Despite the innovation, China still trails leaders like TSMC, which is بالفعل moving toward 2 nm and beyond. Even optimistic projections place Huawei’s equivalent of 1.4 nm density around 2031, potentially leaving a multi-year gap in real-world performance.
Stacking logic layers intensifies heat dissipation issues, as lower layers become trapped beneath upper ones. This creates significant engineering hurdles absent in more conventional stacking approaches, which often separate memory and logic.
Advanced chip design still relies heavily on EDA software from US firms like Synopsys and Cadence. This dependency remains a critical vulnerability, even if hardware constraints are partially mitigated.
Huawei’s efforts align with its push in AI chips, particularly the Ascend series. With Nvidia constrained in China due to export controls, Huawei is filling a growing বাজার gap, supported by domestic AI ecosystems and models optimized for its hardware.
The US model emphasizes ever-larger systems and higher costs, while China’s approach focuses on cost reduction and efficiency, even at the expense of peak performance. This divergence could reshape global AI infrastructure economics.
Huawei’s new scaling framework represents both a technical workaround and a strategic bid to redefine semiconductor leadership, but its long-term impact will depend on real-world manufacturing success and industry adoption.